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the a1260 vertical hall-effect sensor ic is an extremely temperature-stable and stress-resistant magnetic-sensing device ideal for harsh operating environments. the sensor is actuated by alternating north and south polarity magnetic fields in plane with the devices branded face. two package options, the sot23w surface-mount and sip through-hole, allow sensing in a variety of orientations with respect to the mounting position. superior high-temperature performance is made possible through dynamic offset cancellation, which reduces the residual offset voltage normally caused by device overmolding, temperature dependencies, and thermal stress. each device includes on a single silicon chip a voltage regulator, a hall-voltage generator, a small-signal amplifier, chopper stabilization, a schmitt trigger, and a short-circuit protected nmos output to sink up to 25 ma. the on-board regulator permits operation with supply voltages of 3 to 24 v. the advantage of operating down to 3 v is that the device can be used in 3.3 v applications, while allowing additional external resistance in series with the supply pin for greater protection against high-voltage transient events. the output is turned on when a south pole of sufficient strength perpendicular to the vertical hall element is present. a north pole is necessary to turn the output off. package type lh is a modified sot23w surface-mount package that switches with magnetic fields oriented perpendicularly to the non-leaded side of the package. the ua package is an ultra-mini sip, equipped a1260-ds, rev. 2 ? aec-q100 automotive qualified ? magnetic sensing parallel to surface of the package ? highly sensitive switch thresholds ? symmetrical latch switch points ? operation from unregulated supply down to 3 v ? small package sizes ? automotive grade output short-circuit protection resistant to physical stress reverse-battery protection solid-state reliability superior temperature stability supply voltage zener clamp chopper-stabilized precision vertical hall-effect latch packages: functional block diagram not to scale a1260 regulator vcc v ertical hall hall amp sample, hold, &a veraging low-pass filter to all subcircuits control current limit gnd vout dynamic of fset cancellation features and benefits description 3-pin sot23-w (suffx lh) 3-pin sip (suffx ua) continued on next page...
2 absolute maximum ratings characteristic symbol notes rating unit forward supply voltage v cc 26.5 v reverse supply voltage v rcc -18 v output off voltage v out 26 v continuous output current i out 25 ma reverse output current i outr -50 ma operating ambient temperature t a range e -40 to 85 c range l -40 to 150 c maximum junction temperature t j(max) 165 c storage temperature t s -65 to 170 c selection guide part number packing package ambient, t a (c) a1260elhlt-t 7-in. reel, 3000 pieces/reel 3-pin surface mount sot23w -40 to 85 a1260elhlx-t 13-in. reel, 10000 pieces/reel 3-pin surface mount sot23w -40 to 85 a1260llhlt-t 7-in. reel, 3000 pieces/reel 3-pin surface mount sot23w -40 to 150 a1260llhlx-t 13-in. reel, 10000 pieces/reel 3-pin surface mount sot23w -40 to 150 a1260eua-t 1 500 pieces per bulk bag sip-3 through hole -40 to 85 a1260lua-t 1 500 pieces per bulk bag sip-3 through hole -40 to 150 1 please contact allegro for availability. specifications terminal list table symbol pin number lh package ua package description vcc 1 1 power supply to chip vout 2 3 output from circuit gnd 3 2 ground vh 12 3 gnd vcc vout package lh pin-out vh 13 2 gnd vcc vout package ua pin-out pin-out diagrams and terminal list table description (continued) for through-hole mounting and lead forming, that switches when a magnetic field is presented to the top of the package, parallel with the branded face. both packages are rohs-compliant and lead (pb) free (suffix, -t), with 100% matte-tin-plated leadframes. chopper-stabilized precision vertical hall-effect latch a1260 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
3 electrical characteristics : valid over full operating voltage and temperature ranges (unless otherwise specifed) characteristics symbol test conditions min. typ. 1 max. unit 2 supply voltage v cc operating, t j < 165c 3 C 24 v output leakage current i outoff v out = 24 v, b < b rp C C 10 a output saturation voltage v out(sat) i out = 20 ma, b > b op C 230 500 mv output current limit i om b > b op 30 C 60 ma power-on time 3 t po v cc > 3.0 v, b < b rp(min) C 10 g, b > b op(max) + 10 g C C 25 s chopping frequency f c C 800 C khz output rise time 3,4 t r r l = 820 , c s = 20 pf C 0.2 2 s output fall time 3,4 t f r l = 820 , c s = 20 pf C 0.1 2 s supply current i cc C 2.5 4 ma reverse battery current i rcc v rcc = -18 v C C C5 ma supply zener clamp voltage v z i cc = 5 ma; t a = 25c 28 34 C v zener impedance i z i cc = 5 ma; t a = 25c C 50 C magnetic characteristics : valid over full operating voltage and temperature ranges (unless otherwise specifed) characteristics symbol test conditions min. typ. max. unit 2 operate point b op 5 25 50 g release point b rp C50 C25 C5 g hysteresis b hys b op - b rp 20 50 80 g n s z x y 1a figure 1: magnet orientation for switching output on for lh package (panel 1a) and ua package (panel 1b) 1 typical data is at t a = 25oc and v cc = 12 v and it is for design information only 2 1 g (gauss) = 0.1 mt (millitesla). 3 power on time, rise time and fall time are guaranteed through device characterization 4 c s = oscilloscope probe capacitance. 1b n s z x y chopper-stabilized precision vertical hall-effect latch a1260 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
4 thermal characteristics: may require derating at maximum conditions; see application information characteristic symbol notes rating unit package thermal resistance r ja package lh, 2-layer pcb with 0.463 in. 2 of copper area each side connected by thermal vias 110 c/w package lh, 1-layer pcb with copper limited to solder pads 228 c/w package ua, 1-layer pcb with copper limited to solder pads 165 c/w package lh, 2-layer pcb (r = 1 10oc/w) ja package ua, 1-layer pcb (r = 165oc/w) ja package lh, 1-layer pcb (r = 228oc/w) ja v cc(max) v cc(min) 20 40 60 80 100 120 140 160 180 t emperature (oc) maximum allowable v (v) cc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 power derating curve t j(max) = 165oc; i cc = i cc(max) package lh, 2-layer pcb (r = 1 10oc/w) ja package ua, 1-layer pcb (r = 165oc/w) ja package lh, 1-layer pcb (r = 228oc/w) ja 20 40 60 80 100 120 140 160 180 t emperature (oc) maximum power dissipation, p (mw) d 0 100 200 300 400 500 600 700 800 900 1000 1 100 1200 1300 1400 1500 1600 1700 1800 1900 power dissipation versus ambient temperature chopper-stabilized precision vertical hall-effect latch a1260 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
5 electrical operating characteristics 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2 6 10 14 18 22 26 v (v) cc i (ma) cc average supply current versus supply voltage 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 ?60 ?40 ?20 02 04 06 08 0 100 120 140 160 t a (oc) i (ma) cc average supply current versus ambient temperature 400 500 350 450 300 250 200 150 100 50 0 ?60 ?40 ?20 02 04 06 08 0 100 120 140 160 t a (oc) v out(sa t) (mv) average low output voltage versus ambient temperature for i out = 20 ma 400 500 350 450 300 250 200 150 100 50 0 26 10 14 18 22 26 v cc (v) v out(sa t) (mv) average low output voltage versus supply voltage t (oc) a ?40 25 150 v cc (v) 3 12 24 chopper-stabilized precision vertical hall-effect latch a1260 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
6 magnetic operating characteristics 40 45 50 35 30 25 20 15 10 5 0 2 6 10 14 18 22 26 v (v) cc b op (g) average operate point versus supply voltage ?60 ?40 ?20 02 04 06 08 0 100 120 140 160 t a (oc) 40 45 50 35 30 25 20 15 10 5 0 b op (g) average operate point versus ambient temperature ?40 ?45 ?50 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 2 6 10 14 18 22 26 v (v) cc b rp (g) average release point versus supply voltage ?60 ?40 ?20 02 04 06 08 0 100 120 140 160 t a (oc) ?40 ?45 ?50 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 b rp (g) average release point versus ambient temperature 40 30 20 50 60 70 80 2 6 10 14 18 22 26 v (v) cc b hy s (g) average switchpoint hysteresis versus supply voltage 40 30 20 50 60 70 80 b hy s (g) ?60 ?40 ?20 02 04 06 08 0 100 120 140 160 t a (oc) average switchpoint hysteresis versus ambient temperature t c a C40 2 10 v cc v 3 12 24 chopper-stabilized precision vertical hall-effect latch a1260 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
7 functional description operation the output of these devices switches low (turns on) when a south polarity magnetic field perpendicular to the hall-effect sensor exceeds the operate point threshold (b op ). the lh package is offered with a vertical hall element capable of sensing magnetic fields perpendicular to the non-leaded side of the package closest to pin 1. the ua package vertical hall element senses fields per - pendicular to the top of the package opposite of the device leads. the magnetic field is perpendicular to the hall-effect sensor when the direction of the field is parallel to the x-axis for the lh package (see panel 2a in figure 2) and y-axis for the ua pack - age (see panel 2b in figure 2). after turn-on, the output voltage is v out(sat) . the output transistor is capable of sinking current up to the short circuit current limit i om , which is a minimum of 30 ma. the device output goes high (turns off) when the mag - netic field is reduced below the release point (b rp ), which requires a north pole of sufficient strength. removal of the magnetic field will leave the device output latched on if the last crossed switch point is b op , or latched off if the last crossed switch point is b rp . the difference in the magnetic operate and release points is the hysteresis (b hys ) of the device. this built-in hysteresis allows clean switching of the output even in the presence of external mechanical vibration and electrical noise. powering-on the device in the hysteresis range (less than b op and higher than b rp ) will give an indeterminate output state. a valid state is attained after the first excursion beyond b op or b rp . v+ 0 b? 0 b+ v cc v out(sa t) b hys v out switch to low switch to high b rp b op figure 3: switching behavior of latches on the horizontal axis, the b+ direction indicates increasing south polarity magnetic field strength, and the bC direction indicates increasing north polarity magnetic field strength. removal of the magnetic field will leave the device latched in its current state. 2a 2b y x n n s s lh package ua package v ertical hall device magnet magnet figure 2: vertical hall sensing (left) lh package orientation and (right) ua package orientation (not to scale) chopper-stabilized precision vertical hall-effect latch a1260 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
8 v s c byp 0.1 f v dd gnd gnd r load sensor output a1260 out figure 4: typical application circuit applications it is strongly recommended that an external capacitor be con - nected (in close proximity to the hall-effect sensor ic) between the supply and ground of the device to reduce both external noise and noise generated by the chopper stabilization technique. as shown in figure 4, a 0.1 f capacitor is typical. extensive applications information on magnets and hall-effect sensors is available in: ? hall-effect ic applications guide, an27701, ? hall-effect devices: guidelines for designing subassemblies using hall-effect devices an27703.1 ? soldering methods for allegros products C smt and through- hole, an26009 all are provided on the allegro web site: www.allegromicro.com chopper-stabilized precision vertical hall-effect latch a1260 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
9 a limiting factor for switchpoint accuracy when using hall-effect technology is the small-signal voltage developed across the hall plate. this voltage is proportionally small relative to the offset that can be produced at the output of the hall sensor. this makes it difficult to process the signal and maintain an accurate, reliable output over the specified temperature and voltage range. chopper stabilization is a proven approach used to minimize hall offset. the allegro patented technique, dynamic quadrature offset cancellation, removes key sources of the output drift induced by temperature and package stress. this offset reduction technique is based on a signal modulation-demodulation process. figure 5: model of chopper stabilization circuit (dynamic offset cancel - lation) illustrates how it is implemented. the undesired offset signal is separated from the magnetically induced signal in the frequency domain through modulation. the subsequent demodulation acts as a modulation process for the offset causing the magnetically induced signal to recover its original spectrum at baseband while the dc offset becomes a high- frequency signal. then, using a low-pass filter, the signal passes while the modulated dc offset is suppressed. allegros innova - tive chopper stabilization technique uses a high-frequency clock. the high-frequency operation allows a greater sampling rate that produces higher accuracy, reduced jitter, and faster signal processing. additionally, filtering is more effective and results in a lower noise analog signal at the sensor output. devices such as the a1260 that utilize this approach have an extremely stable quiescent hall output voltage, are immune to thermal stress, and have precise recoverability after temperature cycling. this technique is made possible through the use of a bicmos process which allows the use of low offset and low noise ampli - fiers in combination with high-density logic and sample-and-hold circuits. chopper stabilization amp. low-pass filter sample, hold & a veraging regulator clock/logic hall element figure 5: model of chopper stabilization circuit (dynamic offset cancellation) chopper-stabilized precision vertical hall-effect latch a1260 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
10 power derating the device must be operated below the maximum junction tem - perature of the device (t j(max) ). under certain combinations of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the appli - cation. this section presents a procedure for correlating factors affecting operating t j . (thermal data is also available on the allegro microsystems web site.) the package thermal resistance (r ja ) is a figure of merit sum - marizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. its primary component is the effective thermal conductivity (k) of the printed circuit board, including adjacent devices and traces. radiation from the die through the device case (r jc ) is relatively small component of r ja . ambient air temperature (t a ) and air motion are significant external factors, damped by overmolding. the effect of varying power levels (power dissipation, p d ), can be estimated. the following formulas represent the fundamental relationships used to estimate t j , at p d . p d = v in i in (1) ? t = p d r ja (2) t j = t a + ? t (3) for example, given common conditions such as: t a = 25c, v cc = 12 v, i cc = 2.5 ma, and r ja = 110c/w for the lh package, then: p d = v cc i cc = 12 v 2.5 ma = 30 mw ? t = p d r ja = 30 mw 110c/w = 3.3c t j = t a + ? t = 25c + 3.3c = 28.3c a worst-case estimate (p d(max) ) represents the maximum allow - able power level (v cc(max) , i cc(max) ), without exceeding t j(max) , at a selected r ja and t a . example: reliability for v cc at t a = 150c, package lh, using low-k pcb. observe the worst-case ratings for the device, specifically: r ja = 228c/w, t j(max) = 165c, v cc(max) = 24 v, and i cc(max) = 4 ma. calculate the maximum allowable power level, p d(max) . first, invert equation 3: ?t max = t j(max) C t a = 165c C 150c = 15c this provides the allowable increase to t j resulting from internal power dissipation. then, invert equation 2: p d(max) = ?t max r ja = 15c 228c/w = 66 mw finally, invert equation 1 with respect to voltage: v cc(est) = p d(max) i cc(max) = 66 mw 4 ma = 16.4 v the result indicates that, at t a , the application and device can dissipate adequate amounts of heat at voltages v cc(est) . compare v cc(est) to v cc(max) . if v cc(est) v cc(max) , then reli - able operation between v cc(est) and v cc(max) requires enhanced r ja . if v cc(est) v cc(max) , then operation between v cc(est) and v cc(max) is reliable under these conditions. in cases where the v cc(max) level is known, and the system designer would like to determine the maximum allowable ambi - ent temperature (t a(max) ), the calculations can be reversed. for example, in a worst case scenario with conditions v cc(max) = 24 v, i cc(max) = 4 ma, and r ja = 228 c/w using equation 1 the largest possible amount of dissipated power is: p d = v in i in p d = 24 v 4 ma = 96 mw then, by rearranging equations 3: t a(max) = t j(max) C t t a (max) = 165c/w C (96 mw 228c/w) t a (max) = 165c/w C 21.9c = 143.1c in another example, the regulated supply voltage is equal to 3 v. therefore, v cc(max) = 3 v and i cc(max) = 4 ma. by using equa- tion 1 the largest possible amount of dissipated power is: p d = v in i in p d = 3 v 4 ma = 12 mw then, by rearranging equation 3: t a(max) = t j(max) C t t a(max) = 165c/w C (12 mw 228c/w) t a(max) = 165c/w C 2.7c = 162.3c the operating temperature range of the device (t a ) is limited to between -40c and 150c, and in the above case there is suffi - cient power dissipation head room to operate the device through - out this range. in the above example, we are not exceeding the maximum junc - tion temperature; however, performance beyond the maximum operating ambient temperature of 150oc is not guaranteed. chopper-stabilized precision vertical hall-effect latch a1260 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
11 package outline drawing for reference only ?n ot for t ooling use (reference dwg-2840) dimensions in millimeters ? not to scale dimensions exclusive of mold ?ash, gate burrs, and dambar protrusions exact case and lead con?guration at supplier discretion within limits shown a b c d c reference land pattern layout all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances active area depth, 0.28 mm hall elements, not to scale = last three digits of device part number n standard branding reference v iew nnn branding scale and appearance at supplier discretion seating plane gauge plan e pcb layout reference v iew 0.55 ref 0.25 bsc 0.95 bsc 0.95 1.00 0.70 2.40 2 1 b a branded face 2.90 +0.10 ?0.20 44 8x 10 ref 0.180 +0.020 ?0.053 0.05 +0.10 ?0.05 0.25 min 1.91 +0.19 ?0.06 2.98 +0.12 ?0.08 1.00 0.13 0.40 0.10 d d d 0.43 0.96 3 figure 6: package lh, 3-pin sot23-w chopper-stabilized precision vertical hall-effect latch a1260 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
12 for reference only ? not for t ooling use (reference dwg-9013) dimensions in millimeters ? not to scale dimensions exclusive of mold ?ash, gate burrs, and dambar protrusions exact case and lead con?guration at supplier discretion within limits shown a b c d e d branding scale and appearance at supplier discretion hall element, not to scale dambar removal protrusion (6x) gate and tie bar burr area active area depth, 0.50 mm ref nnn standard branding reference v iew = supplier emblem = last three digits of device part numbe r n 1 0.79 ref mold ejector pin indent branded face 0.41 +0.03 ?0.06 c 45 2 x 10 1.52 0.05 23 1 1.27 nom 1.02 max b a e e 2.04 0.425 e 4.09 +0.08 ?0.05 3.02 +0.08 ?0.05 0.43 +0.05 ?0.07 14.99 0.25 45 figure 7: package ua, 3-pin sip chopper-stabilized precision vertical hall-effect latch a1260 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
13 for the latest version of this document, visit our website: www.allegromicro.com revision history revision revision date description of revision C march 10, 2015 initial release 1 july 13, 2015 corrected lh package active area depth value 2 september 21, 2015 added aec-q100 qualification under features and benefits copyright ?2015, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegros products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of allegros product can reasonably be expected to cause bodily harm. the information included herein is believed to be accurate and reliable. however, allegro microsystems, llc assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. chopper-stabilized precision vertical hall-effect latch a1260 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com

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